An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing
The KIPS Transactions:PartB , Vol. 13, No. 3, pp. 223-230, Jun. 2006
10.3745/KIPSTB.2006.13.3.223, PDF Download:
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Cite this article
[IEEE Style]
S. H. Jin, J. U. Cho, K. H. Kwon, J. W. Jeon, "An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing," The KIPS Transactions:PartB , vol. 13, no. 3, pp. 223-230, 2006. DOI: 10.3745/KIPSTB.2006.13.3.223.
[ACM Style]
S. H. Jin, J. U. Cho, K. H. Kwon, and J. W. Jeon. 2006. An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing. The KIPS Transactions:PartB , 13, 3, (2006), 223-230. DOI: 10.3745/KIPSTB.2006.13.3.223.