Design of a Low Power MicroController Core for Intellectual Property applications


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 2, pp. 470-476, Feb. 2000
10.3745/KIPSTE.2000.7.2.470,   PDF Download:

Abstract

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-to-register data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.


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Cite this article
[IEEE Style]
K. Y. Lee and D. Y. Lee, "Design of a Low Power MicroController Core for Intellectual Property applications," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 2, pp. 470-476, 2000. DOI: 10.3745/KIPSTE.2000.7.2.470.

[ACM Style]
Kwang Youb Lee and Dong Yup Lee. 2000. Design of a Low Power MicroController Core for Intellectual Property applications. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 2, (2000), 470-476. DOI: 10.3745/KIPSTE.2000.7.2.470.