Computer Graphics & The Development of PLD Design Tool using the EDIF Netlist


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 4, pp. 1025-1032, Apr. 1998
10.3745/KIPSTE.1998.5.4.1025,   PDF Download:

Abstract

In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms : JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist. FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generating JEDEC file of GAL6001 and GAL 6002, having a forms of EPLD which is bigger than PLD.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
K. H. Seok and B. S. Zoon, "Computer Graphics & The Development of PLD Design Tool using the EDIF Netlist," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 4, pp. 1025-1032, 1998. DOI: 10.3745/KIPSTE.1998.5.4.1025.

[ACM Style]
Kim Hi Seok and Byun Sang Zoon. 1998. Computer Graphics & The Development of PLD Design Tool using the EDIF Netlist. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 4, (1998), 1025-1032. DOI: 10.3745/KIPSTE.1998.5.4.1025.