Lee Jae Hoon, Cho jin Woo, Min Hyoung Bok

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 5, pp. 1371-1379, May. 1997
10.3745/KIPSTE.1997.4.5.1371,   PDF Download:

Abstract

Undetectable faults in a digital circuit are faults that no input patterns can detect. Identifying these faults in test generation process is very time-consuming especially for sequential circuits. In this paper we present a new algorithm to identify undetectable faults in sequential circuits. In the algorithm, we identify uninitializable flip-flops and then, faults that prevent initialization of the flip-flops(FPIs) are identified, finally propagation path of the FPI is checked. Time complexity of this algorithm is proportional to the product of the number of flip flops with at least a self loop and the number of gates in the circuit. Experiments were performed on the ISCAS89 benchmark circuits to show the feasibility of the proposed algorithm. We could identify large amount of undetectable faults (up to 50% of the number of flip-flops) in circuits with uninitializable flip-flops. Considering that most of the time in test generation is consumed in identifying undetectable faults, performance of test generator can be improved by using this algorithm as a pre-processing of test generation.

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