A High Speed Path Delay Fault Simulator for VLSI
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 1, pp. 298-310, Jan. 1997
10.3745/KIPSTE.1997.4.1.298, PDF Download:
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Cite this article
[IEEE Style]
Y. Y. Tae, K. Y. Seok, K. S. Ho, "A High Speed Path Delay Fault Simulator for VLSI," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 1, pp. 298-310, 1997. DOI: 10.3745/KIPSTE.1997.4.1.298.
[ACM Style]
Yim Yong Tae, Kang Yong Seok, and Kang Sung Ho. 1997. A High Speed Path Delay Fault Simulator for VLSI. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 1, (1997), 298-310. DOI: 10.3745/KIPSTE.1997.4.1.298.