High-level Modeling and Test Generation with VHDL for Sequential Circuits


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 5, pp. 1346-1353, Sep. 1996
10.3745/KIPSTE.1996.3.5.1346,   PDF Download:

Abstract

In this paper, we propose a modelin method for the flip-flop and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where branching occurs to one of two micro-operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point(FCON), a test pattern is generated by fault sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL.


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Cite this article
[IEEE Style]
L. J. Min and L. J. Han, "High-level Modeling and Test Generation with VHDL for Sequential Circuits," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 3, no. 5, pp. 1346-1353, 1996. DOI: 10.3745/KIPSTE.1996.3.5.1346.

[ACM Style]
Lee Jae Min and Lee Jong Han. 1996. High-level Modeling and Test Generation with VHDL for Sequential Circuits. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 3, 5, (1996), 1346-1353. DOI: 10.3745/KIPSTE.1996.3.5.1346.