A Design and Implementation of High Speed Hardware Sorter with Reverse Radix Method


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 4, pp. 992-1001, Jul. 1996
10.3745/KIPSTE.1996.3.4.992,   PDF Download:

Abstract

Raix sort scans the data twice in a pass, to search bit 0s of the items being sorted and store them into the lowest address, and to search bit 1s and store them into the following addresses. This doubles the sorting time. In this paper, we introduce Reverse Radix Sort Algorithm, in which the data being sorted are scanned just once and write upward from the lowest address if it is 0 and downward from the highest address if it is 1. The algorithm is simple and the hardware sorter implemented by this method shows very high sorting speed. Hardware implementation requrires two separate pocket memories, register, an upward increasing address counter, a down ward decreasing address counter, and computer. The software simulation of Reverse Radix Sort Algorithm performs sorting in the speed of 54.9ms per 10 thousand of 8 bit digit data, but the hardware sorter spends 5.3 ms to sort the same number of data.


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Cite this article
[IEEE Style]
P. H. Soon, C. J. Yun, K. H. Sook, "A Design and Implementation of High Speed Hardware Sorter with Reverse Radix Method," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 3, no. 4, pp. 992-1001, 1996. DOI: 10.3745/KIPSTE.1996.3.4.992.

[ACM Style]
Park Hee Soon, Chun Jong Yun, and Kim Hee Sook. 1996. A Design and Implementation of High Speed Hardware Sorter with Reverse Radix Method. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 3, 4, (1996), 992-1001. DOI: 10.3745/KIPSTE.1996.3.4.992.