Yang Choong Reol, Kim Jin Tae

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 4, pp. 947-960, Jul. 1996
10.3745/KIPSTE.1996.3.4.947,   PDF Download:

Abstract

The primary goal for developing high performance ATM switching systems is to minimize the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLSI(Very Large Scale Integrated circuit) as the number of input ports increases, the use of switching module method that realizes 32*32, 150Mb/s switch utilizing 8*, 600Mb/s or 16*16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evaluated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure iin outline of 32*32(4.9Gb/s throughput), 150Mb/s switched under research in many countries is proposed, and eventally, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

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