A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 6, pp. 969-973, Nov. 1995
10.3745/KIPSTE.1995.2.6.969,   PDF Download:

Abstract

In this paper, a new parallel multiplier array is proposed to reduce the multiplication time by modifying CSA(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA(doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.


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Cite this article
[IEEE Style]
R. K. Hyeon, "A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 6, pp. 969-973, 1995. DOI: 10.3745/KIPSTE.1995.2.6.969.

[ACM Style]
Rhee Kang Hyeon. 1995. A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 6, (1995), 969-973. DOI: 10.3745/KIPSTE.1995.2.6.969.