Logic Synthesis Algorithm for TLU-Type FPGA


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 5, pp. 777-786, Sep. 1995
10.3745/KIPSTE.1995.2.5.777,   PDF Download:

Abstract

This paper describes several algorithms for technology mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improve the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as node-pair decomposition, merging fanin, unified reduction and multiple output decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique[8]. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
P. J. Hyun and K. B. Gwan, "Logic Synthesis Algorithm for TLU-Type FPGA," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 5, pp. 777-786, 1995. DOI: 10.3745/KIPSTE.1995.2.5.777.

[ACM Style]
Park Jang Hyun and Kim Bo Gwan. 1995. Logic Synthesis Algorithm for TLU-Type FPGA. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 5, (1995), 777-786. DOI: 10.3745/KIPSTE.1995.2.5.777.