MI-MESI Write-invalidate Snooping Cache Coherence Protocol


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 5, pp. 757-767, Sep. 1995
10.3745/KIPSTE.1995.2.5.757,   PDF Download:

Abstract

In this paper, we present MI-MESI write-invalidate snooping cache coherence protocol which addresses several significant drawbacks of MESI and I-MESI write-invalidate snooping cache coherence protocols under the split transaction bus based multiprocessor environment. In this protocol, each cache block maintains one of six cache states which represent Modified-shared, Invalid-by-other, Modified, Exclusive, Shared and Invalid states. By using these cache states, our protocol reduces both the access contention and unnecessary updates for the memory modules significantly, and thus providing the fast memory access time.


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Cite this article
[IEEE Style]
J. S. Tae, "MI-MESI Write-invalidate Snooping Cache Coherence Protocol," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 5, pp. 757-767, 1995. DOI: 10.3745/KIPSTE.1995.2.5.757.

[ACM Style]
Jhang Seong Tae. 1995. MI-MESI Write-invalidate Snooping Cache Coherence Protocol. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 5, (1995), 757-767. DOI: 10.3745/KIPSTE.1995.2.5.757.