Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA
The KIPS Transactions:PartC, Vol. 8, No. 3, pp. 277-286, Jun. 2001
10.3745/KIPSTC.2001.8.3.277, PDF Download:
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Cite this article
[IEEE Style]
K. B. Lee and B. W. Lee, "Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA," The KIPS Transactions:PartC, vol. 8, no. 3, pp. 277-286, 2001. DOI: 10.3745/KIPSTC.2001.8.3.277.
[ACM Style]
Keon Bae Lee and Byung Wook Lee. 2001. Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA. The KIPS Transactions:PartC, 8, 3, (2001), 277-286. DOI: 10.3745/KIPSTC.2001.8.3.277.