Computer Graphics & Energy-Efficient and Parameterized Designs for Fast Fourier Transform on FPGAs


The KIPS Transactions:PartA, Vol. 13, No. 2, pp. 171-176, Apr. 2006
10.3745/KIPSTA.2006.13.2.171,   PDF Download:

Abstract

In this paper, we develop energy efficient designs for the Fast Fourier Transform (FFT) on FPGAs. Architectures for FFT on FPGAs are designed by investigating and applying techniques for minimizing the energy dissipation. Architectural parmeters such as degrees of vertical and horizontal parallelism are identified and a design choices. We determine design trade-offs using high-level performance estimation to obtain energy-efficient designs. We implemented a set storage types as parameters, on Xilinx Vertex-II FPGA to verify the estimates. Our designs dissipate 57% to 78% less energy than the optimized designs from the Xilinx library. In terms of a comprehensive metric such as EAT (Energy-Area-Time), out designs offer performance improvements of 3-13x over the Xilinx designs.


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Cite this article
[IEEE Style]
J. W. Jang, W. J. Han, S. I. Choi, "Computer Graphics & Energy-Efficient and Parameterized Designs for Fast Fourier Transform on FPGAs," The KIPS Transactions:PartA, vol. 13, no. 2, pp. 171-176, 2006. DOI: 10.3745/KIPSTA.2006.13.2.171.

[ACM Style]
Ju Wook Jang, Woo Jin Han, and Seon Il Choi. 2006. Computer Graphics & Energy-Efficient and Parameterized Designs for Fast Fourier Transform on FPGAs. The KIPS Transactions:PartA, 13, 2, (2006), 171-176. DOI: 10.3745/KIPSTA.2006.13.2.171.