Jun Sik Min, Tae Mu Chang

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 12, pp. 3964-3975, Dec. 2000
10.3745/KIPSTE.2000.7.12.3964,   PDF Download:

Abstract

There are two policies for maintaining consistency among the multiple processor caches in a multiprocessor system Write invalidate and Write update. In the write invalidate policy, whenever a processor attempt to write its cached block, it has to invalidate all the same copies of the updated block in the system. As a results of this frequent invalidations, this policy results in high cache miss ratio. On the other hand, the write update policy renew them, instead of invalidating all the same copies. This policy has to transfer the updated contents through interconnection network, whether the updated block is private or not. Therefore the network suffer from heavy transaction traffic. In this paper we present an efficient cache coherence protocol for shared memory multiprocessor system connected by slotted ring. This protocol is based on the write update policy, but the updated contents are transferred only in case of updating the shared block. Otherwise, if the updated block is private, the updated contents are not transferred. We analyze the proposed protocol and enforce simulation to compare it with previous version.

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