Won Gi Kim , Myung Gyun Kim , Sungho Kang , Gunhee Han

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 10, pp. 3226-3235, Oct. 2000
10.3745/KIPSTE.2000.7.10.3226,   PDF Download:

Abstract

delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults effectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification. First, we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator in the circuit. Determining enhanced scan flip-flops are based on a fault coverage or a hardware overhead. Through the experiment for ISCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan environment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

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