Computer Graphics & Bus and Register Optimization in Datapath Synthesis


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 6, No. 8, pp. 2196-2203, Aug. 1999
10.3745/KIPSTE.1999.6.8.2196,   PDF Download:

Abstract

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is a process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital wave filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problem in order to get the optimal scheduling results in the integer linear programming environment.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
S. K. Ho and Y. K. Kan, "Computer Graphics & Bus and Register Optimization in Datapath Synthesis," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 6, no. 8, pp. 2196-2203, 1999. DOI: 10.3745/KIPSTE.1999.6.8.2196.

[ACM Style]
Shinn Kwan Ho and Yi Keun Kan. 1999. Computer Graphics & Bus and Register Optimization in Datapath Synthesis. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 6, 8, (1999), 2196-2203. DOI: 10.3745/KIPSTE.1999.6.8.2196.