Lee Dae Hee, Yang Sae Yang

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 6, No. 6, pp. 1635-1645, Jun. 1999
10.3745/KIPSTE.1999.6.6.1635,   PDF Download:

Abstract

In this paper, an intelligent resynthesis technique for timing optimization at the architecture-level has been studied. The proposed technique can remedy the problem which may occur in combinational timing optimization techniques applied to circuits which have the hierarchical subblock structure at the architectural-level. The approach first tries to maintain the original hierarchical subblock structure while minimizing the lognest delay by retiming and peripheral retiming. If this is unsuccessful, new block boundaries have been formed so that timing optimization for newly constructed individual subcomponent from the partition can result in minimizing the longest delay of whole circuit. This paper tries to find a new approach to timing optimization for circuits which have hierarchical structure at architectural-level, and has verified its effectiveness experimentally. We claim its usefulness from the fact that most designers design the circuits hierarchically due to the increase of design complexity.

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