Jee Sung Hyun, Park No Kwang, Jeon Joong Nam, Kim Suk Il

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 6, No. 5, pp. 1225-1240, May. 1999
10.3745/KIPSTE.1999.6.5.1225,   PDF Download:

Abstract

This paper proposes PASC(PArtitioned SCeduler) processor architecture that equips with a number of functional unit and a individual scheduler pairs. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No Operation) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

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