An Aggressive Register Allocation Algorithm for EPIC Architectures


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 6, No. 2, pp. 497-511, Feb. 1999
10.3745/KIPSTE.1999.6.2.497,   PDF Download:

Abstract

Recently, many parallel processing technologies were developed. ILP(Instruction Level Parallelism) processor's performance have been growed very rapidly. Especially, EPIC(Explicitly Parallel Instruction Computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper, to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.


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Cite this article
[IEEE Style]
C. J. Kee and L. S. Jeong, "An Aggressive Register Allocation Algorithm for EPIC Architectures," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 6, no. 2, pp. 497-511, 1999. DOI: 10.3745/KIPSTE.1999.6.2.497.

[ACM Style]
Choi Joon Kee and Lee Sang Jeong. 1999. An Aggressive Register Allocation Algorithm for EPIC Architectures. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 6, 2, (1999), 497-511. DOI: 10.3745/KIPSTE.1999.6.2.497.