Computer Graphics & A Design of a CMOS Circuit of Asynchronous Adders Based on Carry Selection and Carry Bypass


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 11, pp. 2980-2988, Nov. 1998
10.3745/KIPSTE.1998.5.11.2980,   PDF Download:

Abstract

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than the previous ripple carry adders.


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Cite this article
[IEEE Style]
J. S. Tae, "Computer Graphics & A Design of a CMOS Circuit of Asynchronous Adders Based on Carry Selection and Carry Bypass," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 11, pp. 2980-2988, 1998. DOI: 10.3745/KIPSTE.1998.5.11.2980.

[ACM Style]
Jung Sung Tae. 1998. Computer Graphics & A Design of a CMOS Circuit of Asynchronous Adders Based on Carry Selection and Carry Bypass. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 11, (1998), 2980-2988. DOI: 10.3745/KIPSTE.1998.5.11.2980.