Kim Shin Dug, Kim Young Sik, Han Tack Don

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 10, pp. 2686-2703, Oct. 1998
10.3745/KIPSTE.1998.5.10.2686,   PDF Download:

Abstract

The widening performance gap between processor and memory causes an emergence of the promising architecture, processor-memory (P-M) integration. In this paper, various design issues for P-M integration are studied. First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the performance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the performance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified to be better that the hierarchical multi-bank architecture as well as the conventional bank architecture by execution driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

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